Half Adder in Prolog - Implementation of Half Adder using Prolog Codes
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By Nischal Lal Shrestha

On Friday 2 Feb 2019

Half Adder in Prolog - Implementation of Half Adder using Prolog Codes

/* Author: Nischal Lal Shrestha. Date : 12/5/2018 The half adder adds two single binary digits A and B. It has two outputs, sum (S) and carry (C). The Boolean logic for the sum (in this case S) will be A′B + AB′ i.e X-OR whereas for the carry (C) will be AB i.e AND. The truth table for the half adder is: Inputs Outputs A B C S 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 */ % Facts for AND Gate. and(0, 0, 0). and(0, 1, 0). and(1, 0, 0). and(1, 1, 1). % Facts for XOR Gate. xor(0, 0, 0). xor(0, 1, 1). xor(1, 0, 1). xor(1, 1, 0). % Rule for Half Adder halfAdder(A, B, C, S) :- xor(A, B, S), and(A, B, C). % Reference: https://en.wikipedia.org/wiki/Adder_(electronics)#Half_adder

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